Field of the Invention
The present invention relates in general to memory ownership, and more particularly to determining memory ownership on a cache line basis that may be used for detecting self-modifying code.
Description of the Related Art
Self-modifying code (SMC) includes at least one instruction executed by a local processor that modifies another instruction or instruction sequence that is to be subsequently executed by the processor. SMC may include a sequence of code that modifies code that has just been executed, in which case the modified code is executed again with a newly modified function. SMC may further include the case in which code is modifying code just ahead and staying just in front of execution. Although SMC may not be as common today as in the past, many legacy programs include SMC and should be executed properly. A processor must be capable of detecting SMC and correcting operation to avoid improper results. The term “processor” as used herein refers to any type of processing unit, including a microprocessor, a central processing unit (CPU), a processing core, a microcontroller, etc. The term “processor” as used herein also includes any type of processor configuration, such as processing units integrated on a chip or integrated circuit (IC) including those incorporated within a system of a chip (SOC) or the like.
Modern processors often perform prefetch operations in which one or more lines of memory are read into an instruction cache (icache). The cache lines from the icache are then parsed into instructions that are forwarded for execution. In order to maximize efficiency, a fetch unit or the like attempts to fill the icache and keep it full to ensure that instructions are continuously available for execution. In order to maximize performance, it is usually desired to keep the execution pipelines as full as possible. Modern processors usually perform out-of-order (OOO) execution in which a later received instruction that is ready for execution may be executed before an earlier instruction that is not ready for execution. At least one problem with prefetch and OOO operation is that instructions that have been prefetched and forwarded for execution may be subsequently modified by SMC. Thus, an instruction that is already sent for execution may have missed the modification potentially causing improper or unintended operation.
Modern processors need to detect and/or prevent completion of stale instructions that were not intended to be executed since modified by code. Processors generally divide ownership of the memory into an instruction area owned by the icache and a data area owned by a data cache (dcache). The instruction area is supposed to contain only instructions for execution and the data area is supposed to be available for storing data and information for a software program. If the icache attempts to read from memory owned by the dcache, ownership must be transferred from the dcache which is a slow and tedious process which tends to serialize operation.
In conventional configurations, ownership was based on page boundaries. A common page size is 4 kilobytes (KB). Although 4 KB is not a significant amount of memory, SMC may cause thrashing of ownership between the icache and the dcache substantially reducing operating efficiency. One solution was to decrease ownership size to one-quarter page, such as 1 KB ownership granularity for a page size of 4 KB. It has been observed that even 1 KB ownership granularity was still problematic for SMC in many situations. Furthermore, larger page sizes are often used, such as 2 megabytes (MB) or even 1 gigabyte (GB), so that ownership granularity has remained a significant issue that reduces overall performance.